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MPC17529 Rev 2.0, 09/2005
0.7 A Dual H-Bridge Motor Driver with 3.0 V/5.0 V Compatible Logic I/O
The 17529 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar step motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17529 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 V- and 5.0 Vcompatible logic). The device features on-board charge pump, as well as built-in shoot-through current protection and an undervoltage shutdown function. The 17529 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17529 has a low total RDS(ON) of 1.2 (max @ 25C). The 17529's low output resistance and high slew rates provide efficient drive for many types of micromotors. Features * Low Total RDS(ON) 0.7 (Typ), 1.2 (Max) @ 25C * Output Current 0.7 A (DC), 1.4 A (Peak) * Shoot-Through Current Protection Circuit * 3.0 V/ 5.0 V CMOS-Compatible Inputs * PWM Control Input Frequency up to 200 kHz * Built-In Charge Pump Circuit * Low Power Consumption * Undervoltage Detection and Shutdown Circuit * Pb-Free Packaging Designated by Suffix Code EV
17529
DUAL H-BRIDGE
EV SUFFIX (PB-FREE) 98ASA10616D 20-TERMINAL VMFP
ORDERING INFORMATION
Device MPC17529EV/EL Temperature Range (TA) -20C to 65C Package 20 VMFP
5.0 V
5.0 V
17529 VDD VM 1/2 C1L C1H C2L OUT1A C2H CRES OUT1B IN1A IN1B IN2A IN2B OE GND OUT2A OUT2B
S
N
MCU
Bipolar Step Motor
PGND1/2
Figure 1. 17529 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CRES C2H C1H C1L C2L LowVoltage Shutdown Charge Pump
VDD
VM1
IN1A
H-Bridge
OUT1A OUT1B
IN1B VDD Level Shifter Predriver PGND1 VM2
OE
Control Logic
IN2A OUT2A
H-Bridge
OUT2B
IN2B
LGND
PGND2
Figure 2. 17529 Simplified Internal Block Diagram
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TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
VDD
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
LGND IN2A IN2B VM2 OUT2B PGND2 OUT1B C2L C1L C1H
IN1A IN1B OE OUT2A PGND1 OUT1A VM1 CRES C2H
Figure 3. 17529 Terminal Connections Table 1. Terminal Function Description
Terminal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name
VDD
Formal Name Control Circuit Power Supply Logic Input Control 1A Logic Input Control 1B Output Enable H-Bridge Output 2A Power Ground 1 H-Bridge Output 1A Motor Drive Power Supply 1 Predriver Power Supply Charge Pump 2H Charge Pump 1H Charge Pump 1L Charge Pump 2L H-Bridge Output 1B Power Ground 2 H-Bridge Output 2B Motor Drive Power Supply 2 Logic Input Control 2B Logic Input Control 2A Logic Ground
Definition Positive power source connection for control circuit. Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). Logic output Enable control of H-Bridges (Low = True). Output A of H-Bridge channel 2. High-current power ground 1. Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Internal triple charge pump output as predriver power supply. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 2 (negative pole). Output B of H-Bridge channel 1. High-current power ground 2. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). Low-current logic signal ground.
IN1A IN1B OE OUT2A PGND1 OUT1A VM1 CRES C2H C1H C1L C2L OUT1B PGND2 OUT2B VM2 IN2B IN2A LGND
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device.
Rating Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage Driver Output Current Continuous Peak (1) ESD Voltage Human Body Model (2) Machine Model (3) Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Thermal Resistance Power Dissipation
(4)
Symbol VM VCRES VDD VIN IO IOPK VESD1 VESD2 TJ TA TSTG RJA PD
Value -0.5 to 8.0 -0.5 to 14 -0.5 to 7.0 -0.5 to VDD + 0.5 0.7 1.4
Unit V V V V A
V 1500 200 -20 to 150 -20 to 65 -65 to 150 120 1040 260 C C C C/W mW C
(5) (6)
Soldering Temperature
TSOLDER
Notes 1. TA = 25C, 10 ms pulse at 200 ms interval. 2. 3. 4. 5. 6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). Mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB). TA = 25C. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted.
Characteristic POWER (VM1, VM2, VDD) Motor Supply Voltage Logic Supply Voltage Driver Quiescent Supply Current (No Signal Input) Logic Quiescent Supply Current (No Signal Input) (7) Operating Power Supply Current Logic Supply Current (8) Charge Pump Circuit Supply Current (9) Low VDD Detection Voltage
(10) (11)
Symbol
Min
Typ
Max
Unit
VM VDD IQM IQVDD IDVDD ICRES VDDDET RDS(ON)
2.0 2.7 - -
5.0 5.0 - -
6.8 5.6 1.0 1.0
V V A mA mA
- - 1.5 -
- - 2.0 0.7
3.0 0.7 2.5 1.2 V Ohms
Driver Output ON Resistance
GATE DRIVE (C1L - C1H, C2L - C2H, CRES) Gate Drive Voltage Recommended External Capacitance (C1L - C1H, C2L - C2H, CRES - GND) CONTROL LOGIC (OE, N1A, N1B, N2A, N2B) Logic Input Voltage Logic Inputs (2.7 V < VDD < 5.7 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current
OE Terminal Input Current Low
I
VCRES CCP
12 0.01
13 0.1
13.5 1.0
V F
VIN VIH VIL IIH IIL
OILOE
0.0
-
VDD - VDD x 0.3 1.0 - 100
V
VDD x 0.7 - - -1.0 -
- - - - 50
V V A A A
Notes 7. 8. 9. 10. 11. IQVDD includes the current to predriver circuit. IVDD includes the current to predriver circuit at fIN = 100 kHz. At fIN = 20 kHz. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate voltage VCRES is applied from an external source, VCRES = 7.5 V. Source + sink at IO = 0.7 A.
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted.
Characteristic INPUT (IN1A, IN1B, OE, IN2A, IN2B) Pulse Input Frequency Input Pulse Rise Time
(12)
Symbol
Min
Typ
Max
Unit
f IN tR tF
- - -
- - -
200
(13)
kHz s s
1.0
(13)
Input Pulse Fall Time (14) OUTPUT (OUT1A, OUT1B, OUT2A, OUT2B) Propagation Delay Time (15) Turn-ON Time Turn-OFF Time Charge Pump Wake-Up Time Low-Voltage Detection Time Notes 12. 13. 14. 15. 16. Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load of Output is 8.0 resistance. CCP = 0.1 F.
(16)
1.0
t PLH t PHL
t VGON tVDDDET
s - - - - 0.1 0.1 1.0 - 0.5 0.5 3.0 10 ms ms
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TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2, OE
VDD 50%
tPLH
OUTA, OUTB 90% 10%
tPHL
t VGON
11 V
VCRES
Figure 4. tPLH, tPHL, and tPZH Timing
Figure 6. Charge Pump Timing Diagram
V
DDDETON
2.5 V/3.5 V 50%
V
DDDETOFF
VDD 0.8 V/ 1.5 V
tVDDDET
tVDDDET
90% IM 0% (<1.0 A)
Figure 5. Low-Voltage Detection Timing Diagram Table 5. Truth Table
INPUT OE L L L L H IN1A IN2A L H L H X IN1B IN2B L L H H X OUT1A OUT2A L H L Z Z OUTPUT OUT1B OUT2B L L H Z Z
H = High. L = Low. Z = High impedance. X = Don't care. OE terminal is pulled up to VDD with internal resistance.
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SYSTEM / APPLICATION INFORMATION INTRODUCTION
SYSTEM / APPLICATION INFORMATION
INTRODUCTION
The 17529 is a monolithic dual H-Bridge ideal for portable electronic applications to control bipolar step motors and brush DC motors such as those found in camera lens assemblies, camera shutters, optical disk drives, etc. The 17529 operates from 2.0 V to 6.8 V, providing dual H-bridge motor drivers with parallel 3.0 V- or 5.0 V-compatible I/O. The device features an on-board charge pump, as well as built-in shoot-through current protection and undervoltage shutdown. The 17529 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) 1.2 . The 17529 can simultaneously drive two brush DC motors or, as shown in the simplified application diagram on page 1, one bipolar step motor. The drivers are designed to be PWM'ed at frequencies up to 200 kHz.
FUNCTIONAL TERMINAL DESCRIPTION CONTROL CIRCUIT POWER SUPPLY (VDD)
The VDD terminal carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals.
MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)
The VM terminals carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the loads attached between the output terminals. All VM terminals must be connected together on the printed circuit board.
CHARGE PUMP (C1L AND C1H, C2L AND C2H)
These two pairs of terminals, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 F.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND IN2B)
These logic input terminals control each H-Bridge output. IN1A logic HIGH = OUT1A HIGH. However, if all inputs are taken HIGH, the outputs bridges are both tri-stated (refer to Table 5, Truth Table, page 7).
PREDRIVER POWER SUPPLY (CRES)
The CRES terminal is the output of the internal charge pump. Its output voltage is approximately three times the VDD voltage. The VCRES voltage is power supply for internal predriver circuit of H-Bridges.
OUTPUT ENABLE (OE)
The OE terminal is a LOW = TRUE enable input. When OE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A, and OUT2B) are tri-stated (high-impedance), regardless of logic input (IN1A, IN1B, IN2A, and IN2B) states.
POWER GROUND (PGND)
Power ground terminals. They must be tied together on the PCB.
H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND OUT2B)
These terminals provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17529 Simplified Internal Block Diagram, page 2).
LOGIC GROUND (LGND)
Logic ground terminal.
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Analog Integrated Circuit Device Data Freescale Semiconductor
This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values
APPLICATIONS FUNCTIONAL TERMINAL DESCRIPTION
APPLICATIONS
TYPICAL APPLICATION
Figure 7 shows a typical application for the 17529. When applying the gate voltage to the CRES terminal from an external source, be sure to connect it via a resistor equal to, or greater than, RG = VCRES / 0.02 . The internal charge pump of this device is generated from the VDD supply; therefore, care must be taken to provide sufficient gate-source voltage for the high-side MOSFETs when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side MOSFET channels. 5.0 V 17529
V CRES < 14 V RG > VCRES /0.02 RG
NC NC NC NC
C1L C1H C2L C2H CRES
VDD
VM
OUT1A
0.01 F
OUT1B
MCU
IN1A IN1B IN2A IN2B
OE
OUT2A
OUT2B
GND
NC = No Connect
Figure 7. 17529 Typical Application Diagram
CONDUCTED ELECTROMOTIVE FORCE (CEMF) SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply terminal (VM) (see Figure 8).
5.0 V 5.0 V 175XX VDD VM C1L C1H C2L C2H CRES OUT GND OUT 5.0 V 5.0 V 175XX VDD VM C1L C1H C2L C2H CRES OUT
PCB LAYOUT
When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground terminals to ensure proper filtering from transients. For all high-current paths, use wide copper traces and shortest possible distances.
OUT
GND
Figure 8. CEMF Snubbing Techniques
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APPLICATIONS PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below.
.
EV (Pb-FREE) SUFFIX 20-LEAD VMFP PLASTIC PACKAGE 98ASA10616D ISSUE A
17529
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision 2.0
Date 9/2005
Description of Changes * * Implemented Revision History page Converted to Freescale format
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MPC17529 Rev 2.0 09/2005

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